Automotive Electronics

Both. RDS(on) × I²rms dominates conduction loss, while Qg × VGS × fsw sets drive power and heating; then check Qrr and Coss. Frequency decides the trade-off — high frequency favors low Qg, low-frequency high-current favors low RDS(on) — and the SGT process lowers both together. Integrated-MOS rectifiers lock on-resistance and voltage rating to one part number; a discrete MOSFET is more flexible. The LV/MV MOSFET category lists Qg_Typ and Coss_Typ columns for comparison.

During inrush the MOSFET sits in its linear region and must absorb VDS × ID for milliseconds to tens of milliseconds; what it survives is set by the SOA curve and EAS, not RDS(on). Ordinary low-RDS(on) parts have poor thermal stability there and can run into local thermal runaway; linear SGT parts are optimized for linear-mode operation with a wider SOA. Example: 48V input, current held to 2A within 8ms — read the 10ms SOA curve directly. SMT10T03DHP/DHSS/DHTS come in PDFN5060-8L, TO220-3L and TO263-3L.

RDS(on) depends on gate-drive voltage, so datasheets grade it at VGS = 10V, 4.5V and 2.5V, and one device's figures can differ a lot between grades. Read the grade that matches your actual drive voltage; a gate driven directly at logic level should use the 2.5V column. Ordering on the lowest 10V figure leaves you with a much higher real resistance under low-voltage drive. Use the Max value, not Typ, for thermal budgeting. The LV/MV MOSFET and wafer categories on this site list Typ/Max at all three grades.

SGT adds a shield electrode beside the trench gate to cut gate-drain capacitance and the Miller effect, giving low switching loss; it covers low-to-medium voltage (about 12V–230V in the catalog) for synchronous rectification, battery management, motor drive and load switches. Superjunction uses vertical charge balance to raise the rating while keeping on-resistance low, covering roughly 300V–800V for off-line supplies, adapters and industrial power. The routes complement rather than replace each other: low-voltage high-frequency designs weigh switching loss and drive matching; medium-to-high voltage designs weigh voltage margin and avalanche energy.

Both — set the margin against the stacked peak. Start from the highest steady bus: the line-voltage upper limit, plus ripple on a PFC output. Add the switching spike from leakage inductance and parasitics, taken from measurement or simulation rather than a rule of thumb. Then keep extra margin for temperature and aging. Choosing the VDS class from steady bus voltage alone is a common HV MOSFET mistake. The HV MOSFET category on this site spans roughly 300V–800V and filters directly on VDS_Max.

It depends on topology and conduction mode. A conventional boost PFC works with a 650V superjunction switch, and swapping the boost diode for a 650V SiC SBD removes reverse-recovery loss — listed SiC SBDs carry Qc of about 9.5nC~28nC, the main source of the switching-loss gap versus silicon FRDs. Totem-pole bridgeless PFC in CCM hard-commutates the body diode; a superjunction body diode carries too much reverse-recovery charge and only suits CrM, so CCM totem-pole needs SiC MOSFETs.

First check whether the power tier and topology are standard. Low-power or single-phase designs (roughly below 20 A) suit discrete IGBTs with external drivers and free layout; three-phase designs above about 30 A suit modules — shared baseplate cooling, low parasitic inductance, isolation and creepage already engineered. Then ask two more questions: can the team develop its own drive and protection circuitry, and is maintenance a whole-module swap or a single-device repair? Listed discretes cover about 15A~150A, modules 15A~950A.

Within one voltage class, a part with lower VCE(sat) usually has a longer turn-off tail and higher Eoff. Drives at 4~16 kHz carrier lean towards low VCE(sat); high-frequency welders and UPS links lean towards low Eon+Eoff. Sum conduction and switching loss at the real carrier frequency, then check junction temperature through Rth(J-C). Align test conditions before comparing: VCE(sat) moves with gate voltage and junction temperature, and switching loss is usually quoted at Tj=125°C, so figures taken under different conditions are not directly comparable.

Three-level topologies expose each switch to only half the bus voltage, so 650V devices can serve a 1000V DC bus with lower switching loss and lower output harmonics. The trade-off is twice the device count and drive channels, which is why dedicated three-level modules are used to contain size and layout. Set the voltage class from the maximum DC-bus voltage plus margin — listed PV and ESS modules come in 650V and 1200V classes — then filter the IGBT module category by the 3-Level configuration.

An IPM packs six IGBTs, freewheeling diodes, gate drive, under-voltage and over-current protection into one DIP module with isolation and creepage already engineered, removing driver design and layout debugging. Listed IGBT-based IPMs are 600V class, rated 6A~30A with 12A~60A peaks — the range of air-conditioner and washer inverter boards. The trade-off: drive timing and gate-resistor knobs are fixed and protection thresholds preset, so check the application level against actual conditions; only high-power or unusual topologies go back to discrete parts.

Listed discrete IGBTs have Vth of about 4.0V~6.5V, and datasheet VCE(sat) is specified at VGE=15V. Drive the gate to that test voltage; MOSFET-style levels give incomplete turn-on and a VCE(sat) off spec. For turn-off stay below the Vth minimum, with a negative bias for margin against false turn-on. Size drive current from gate charge: listed isolated drivers span 3.0/6.0A to 12.0/12.0A, with source and sink checked separately.

Check the current tier first: pick ICP (listed about 12A~60A) from motor start-up and stall peaks, not rated power alone. Then the structure: RC-IGBT is reverse-conducting with higher integration; IGBT&FRD uses a separate freewheeling diode whose recovery behavior can be chosen on its own. Freewheel-side VF of about 1.5V~2.35V and Trr of about 0.15~0.3μs set freewheeling loss and commutation EMI — weigh them by carrier frequency and EMI targets. The two are not drop-in equivalents; re-evaluate recovery behavior when swapping.

Set Viso by the required safety insulation class: the catalog offers 3000Vrms and 5000Vrms, chosen for functional or reinforced insulation — higher is not better. Passing the withstand rating says nothing about common-mode immunity, so check CMTI separately: SineSemi automotive dual-channel parts come in 100 and 150kV/µs tiers, and a shortfall causes false triggering. Drive current likewise: IOH/IOL is 4.0/6.0A or 4.0/7.0A, source and sink asymmetric, so size turn-on and turn-off separately from the switch's gate charge.

Order-of-magnitude: peak gate current I ≈ Qg ÷ target switching time. Then check the driver's IOH (source) and IOL (sink) separately — they are often asymmetric — and leave margin for the external gate resistor. Too little current stretches the switching interval and raises loss. Catalog references: isolated drivers span IOH/IOL 3.0/6.0A to 12.0/12.0A; LV/MV MOSFET Qg runs about 0.8nC~347nC, so a switch change means recalculating.

Bootstrap and level-shifting provide high/low-side switching, not safety isolation: a non-isolated driver shares the control ground and suits low-voltage buses or simple reference potentials. An isolated driver puts a rated insulation barrier between control and power sides; when the bus needs safety protection or a functional-safety partition, bootstrap cannot substitute. Also separate working voltage, transient withstand, and functional versus reinforced insulation — the Viso figure alone does not settle it. Board creepage and clearance must still be met separately.

A protocol-only (PD Source) IC handles CC-line communication and power negotiation, leaving output regulation to an external DC-DC or flyback loop; it can be reused across power platforms, but the power stage must track protocol commands during power steps. An integrated IC combines protocol negotiation with part of the power control, shrinking BOM and footprint — suited to single-port, fixed-power designs, with the power range locked by the chip. Multi-port designs also need dynamic allocation and port priority. Filter the PD category by type and port.

For low-power designs where BOM matters most, choose an integrated part: the built-in 650V MOSFET or GaN removes external switch selection and layout; integrated-switch on-resistance spans 0.15~6Ω, and the 200kHz tier appears only on GaN parts. The cost is a power ceiling fixed by the integrated switch — a new power tier often means a new IC. To choose the switch RDS(on) and package yourself, or reuse one controller across tiers, use a discrete controller with an external MOSFET/GaN. Power ratings follow each datasheet.

Catalog parts span 65~200kHz. Higher frequency shrinks the transformer but raises switching loss and EMI difficulty; the 65kHz tier suits cost-first designs, 130~200kHz suits compact ones. Control mode sets load coverage: QR (quasi-resonant) varies frequency with load to cut switching loss and noise; CCM/QR/DCM combinations cover a wider load range, while single-QR parts target one power tier. Comparing only the frequency figure while ignoring how mode affects light-load efficiency and EMI is a common mistake.

Choose the class from output voltage plus transformer reflected voltage, with margin — output voltage alone misses the reflected voltage and ringing spikes; listed classes are 40V/60V/80V/100V. Then check: RDS_ON of roughly 9~14mΩ, going low for high-current tiers and verifying temperature rise; and timing — minimum on-time 0.7~1.0μs, minimum off-time 0.3~2.5μs — which governs false turn-on and early-off at high frequency and light load, and must suit the primary controller's narrowest pulse. Use DFN 5x6 for high-current tiers; SOP runs short on heat dissipation.

Rated pmax_w is a peak, not what every port gets at once. Catalog parts span 18~100W: 70W is the highest multi-port tier and 100W appears only on single-port 1C parts. Multi-port parts (A+C, 2C+1A and similar) add power-allocation and port-priority logic, so the peak figure alone overstates real experience. Then check QC3.0+ and UFCS support item by item — a failed handshake drops to the lowest rate, the usual cause of "not reaching rated power". Filter the PD category by port and PMAX.

The BCon sends per-zone dimming data and timing to the driver over the SPB interface; mismatched generations cannot communicate. Two generations are listed: SPB-2M without SCK, 10~36 lanes, 500~12000 zones at 120Hz; SPB-16M with SCK, 6~36 lanes, 500~18000 zones — the same lane count gives different zone counts. Match the driver to the BCon generation first, then check channel count (4/8/16) and dimming bit depth.

Rule of thumb: GBW should be at least 5–10× the signal's highest frequency; closed-loop bandwidth ≈ GBW ÷ gain, so size high-gain stages from the closed-loop figure, not open-loop GBW. Catalog parts span 0.01–10MHz GBW and 0.5–1100μA Iq — the power-versus-speed trade-off: low Iq saves power, but SR and GBW usually fall with it, so don't chase the lowest Iq alone. Set the GBW floor from frequency and gain, bound Iq by power budget, then check SR against swing and pick the VOS tier for accuracy.

With noisy or slow-edge signals, a comparator without hysteresis toggles repeatedly near the threshold; some catalog parts build in about 3–3.5mV, the rest need an external hysteresis network. tpd and Iq trade off clearly: the 0.418μA tier sits at 5600ns, while the 160μA tier reaches 73ns. Fast overcurrent protection wants low tpd; slow signals such as battery-voltage monitoring want high tpd and low Iq. Check whole-device current for multi-channel parts, and the output stage (push-pull or open-drain), on the datasheet.

An LDO turns its entire dropout into heat: dissipation ≈ (Vin − Vout) × Iload. Pick the 100/150/250/1000mA tier by peak load current — sizing by the average lets transients sag out of regulation. At large dropout and high current the LDO is just a resistor-heater, so buck first with a DC-DC, then clean up with the LDO, and confirm the package can shed the estimated heat. On battery standby paths check Iq; the TS6122 series goes down to 2μA.

The version number describes the protocol feature set; link performance depends on the stack implementation. Catalog Bluetooth 5.2 SoCs are tri-mode BR + BLE + 2.4G proprietary, and the proprietary mode wins on latency and power — low-latency transparent links need it, and a "5.2" label alone won't confirm support. +12dBm TX and -99dBm sensitivity @BLE 1Mbps set the link budget, but real range also depends on antenna efficiency. Pinouts differ between packages of one part number — don't reuse an old footprint blindly.

"Encryption supported" is not a checkable spec; certification checks each algorithm and key length item by item. For finance and government projects, verify the Chinese national algorithms SM2/SM3/SM4 first; Bluetooth version and financial-grade security are separate matters — take security capability from the datasheet and certifications. Then confirm the 512KB/1MB secure Flash holds firmware plus key partitions, since outgrowing it blocks later OTA expansion. Finally choose BLE-only or dual-mode by the host: POS terminals and printers on legacy hosts need dual-mode.

Payment terminals lock the EMV level to the acquirer's requirement; EMV 3.0 tracks the newer contactless spec, while non-payment readers can use either grade. Short read range is usually not the chip: tune the antenna and matching network to the IC's output stage, and keep the 3.3V rail clean — decoupling quality moves range, and sharing the rail with noisy digital loads cuts sensitivity. Band sets the ecosystem first: HF ISO14443/15693 reads on phones, UHF ISO18000-6C needs a dedicated reader.

"-12" marks a 12-inch wafer format; for most part numbers, the same name without it is the 8-inch version. The gross-die range in the guide is counted per 8" wafer, so confirm the wafer format first, then run cost from gross die. Bare-die selection also checks process and channel configuration, RDS(on) at your gate-drive VGS grade, die size, thickness grade and ESD integration — and never infers die RDS(on) from a packaged part, since package resistance is a real share.

All three sit in the wafer category's parameter columns. Wafer Thickness is the thinning grade — catalog values run from 60±10 to 200±20 μm — chosen to match the packaging or sintering process; a mismatch shows up as warpage or cracking at reflow or sintering. Die Size is given in μm×μm, from about 320×310 to 7000×7450. Gross Die is the die count per wafer, from hundreds to hundreds of thousands on 8", and drives per-die cost and capacity planning.

Qualification answers "can it be used"; stable volume production needs three more checks. First, parameter drift and derating across the operating temperature range — how far RDS(on) and drive thresholds move sets margin at the hot and cold ends. Second, predictable failure modes: stable UVLO and overcurrent thresholds on driver ICs, controlled failure paths under avalanche or short circuit on power devices, verified against real conditions. Third, lot-to-lot consistency and transparent change control. Power modules add power-cycling life; automotive parts replacing industrial ones need item-by-item interface checks.

Open a category page (for example /products/lv-mv-mosfet) to enter Parametric Search. Filters cover brand, product grade (Automotive / Industrial / Consumer) and min/max ranges per parameter. "Columns" sets the visible columns, with part number, brand and grade always shown; "Export CSV" always includes every column regardless of that setting. A note saying "N more parts are not labeled for these parameters" means those parts carry no value on that dimension and are left out — ask an engineer to confirm them.

On the Cross-Reference page, enter the competitor or OEM part number, brand and application; engineers manually check parameters, package and certification requirements and reply by email — a reviewed result, not an instant online answer or a supply commitment. Several parts can go through the BOM page line by line. Qualifying a substitute takes three stages: parameter matching (voltage rating, on-resistance, switching, package and pinout, item by item); small-batch validation (temperature cycling, burn-in, EMC, extended running); phased rollout with the original design kept as backup.

Typ is the typical figure, good for estimates; Max is the worst case, and thermal design and margins use Max. The test condition matters as much as the value: MOSFET RDS(ON) is graded by VGS; SiC parts list 25°C and 175°C sets, so take the one at your highest junction temperature; IGBT-module VCE(sat) is a typical value @VGE=15V, and figures at different gate voltage or Tj can't be compared directly. On-site column names carry the condition, so compare like columns after CSV export.