SMP4002ALPWQ product image

Product Detail

SMP4002ALPWQ

SineSemi 中晶新源Core Authorized Distributor

LV & MV MOSFETsAutomotivePDFN5060-8L-WHOT

Specifications

Package
PDFN5060-8L-W
Configuration
P
VDS_Max
-40 V
ID
-190 A
RDS(ON)_Max @VGS=10V
2.5 mΩ
Automotive (Y/N)
Y
VGS(th)_Typ
-1.8 V
RDS(ON)_Typ @VGS=10V
1.9 mΩ
RDS(ON)_Typ @VGS=4.5V
3.3 mΩ
RDS(ON)_Max @VGS=4.5V
4.6 mΩ
VGS_Max
±20 V
Tj
175 °C
EAS_Max
1000 mJ
Ciss_Typ
6004 pF
Coss_Typ
3216 pF
Crss_Typ
109 pF
Qg_Typ
80 nC

Online Datasheet

Compiled from the manufacturer's datasheet; the official document prevails.

SMP4002ALPWQ

-40V P-Channel Enhancement Mode Power MOSFET

Sinesemi Automotive MOSFET — AEC-Q101 Qualified, PPAP Capable, 175°C Operating Temperature

Product Summary
VDS RDS(ON), max ID, max
-40 V 2.5 mΩ @ VGS = -10V -190 A
4.6 mΩ @ VGS = -4.5V

PDFN5060-8L-W

Features
  • P-Channel Enhancement Mode - Logic Level
  • AEC-Q101 Qualified, PPAP Capable
  • 175°C Operating Temperature
  • 100% ∆VDS & UIS & Rg Tested
Application
  • General Automotive Applications
Mechanical Data
  • Green Molding Compound
  • Moisture Sensitivity: Level 1 per J-STD-020
  • UL Flammability Classification Rating 94V-0
Ordering Information
Orderable Part Number Package Type Device Marking Form Quantity (pcs)
SMP4002ALPWQ PDFN5060-8L-W P4002ALQ 13" Tape&Reel 5,000
Maximum Ratings (@ TA = 25°C, unless otherwise specified.)
Parameter Symbol Value Unit
Drain - Source Voltage VDS -40 V
Gate - Source Voltage VGS ±20 V
Continuous Drain Current (VGS = -10V) (1) ID TA = 25°C: -190 A
TA = 100°C: -134 A
Pulsed Drain Current (2) IDM -759 A
Single Pulse Avalanche Energy (3) EAS 1000 mJ
Single Pulse Avalanche Current (L = 0.1mH) IAS -40 A
Power Dissipation PD TA = 25°C: 158 W
TA = 100°C: 79 W
Junction & Storage Temperature Range TJ, TSTG -55 ~ +175 °C
Thermal Characteristics
Parameter Symbol Typ Max Unit
Thermal Resistance, Junction-to-Ambient (4) R_θJA 32 40 °C/W
Thermal Resistance, Junction-to-Case (5) R_θJC 0.73 0.95 °C/W

Electrical Characteristics (@ TJ = 25°C, unless otherwise specified.)

Off Characteristics (7)
Parameter Symbol Test Condition Min Typ Max Unit
Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250µA -40 V
Zero Gate Voltage Drain Current IDSS VDS = -40V, VGS = 0V -1.0 µA
TJ = 125°C -100 µA
Gate-Source Leakage Current IGSS VGS = ±20V, VDS = 0V ±100 nA
On Characteristics (7)
Parameter Symbol Test Condition Min Typ Max Unit
Gate Threshold Voltage VGS(th) VDS = VGS, ID = -250µA -1.2 -1.8 -2.5 V
Static Drain-Source On-Resistance RDS(on) VGS = -10V, ID = -20A 1.9 2.5
VGS = -4.5V, ID = -15A 3.3 4.6
Forward Transconductance gfs VDS = -5.0V, ID = -20A 81 S
Diodes Forward Voltage VSD IS = -2.0A, VGS = 0V -0.7 -1.2 V
Dynamic Characteristics (7)
Parameter Symbol Test Condition Min Typ Max Unit
Input Capacitance Ciss VDS = -20V, VGS = 0V, f = 1MHz 6004 7805 pF
Output Capacitance Coss 3216 4180 pF
Reverse Transfer Capacitance Crss 109 218 pF
Gate Resistance Rg VGS = 0V, VDS = 0V, f = 1MHz 5.1 Ω
Switching Characteristics (7)
Parameter Symbol Test Condition Min Typ Max Unit
Turn-On Delay Time td(on) VGS = -10V, VDS = -20V 5.8 ns
Rise Time tr ID = -20A, RGEN = 3.0Ω 15 ns
Turn-Off Delay Time td(off) 105 ns
Fall Time tf 36 ns
Gate Charge Characteristics (7)
Parameter Symbol Test Condition Min Typ Max Unit
Total Gate Charge (VGS = -10V) Qg VDS = -20V, ID = -20A 80 104 nC
Total Gate Charge (VGS = -4.5V) Qg 38 47 nC
Gate-Source Charge Qgs VGS = -10V 18.2 24 nC
Gate-Drain Charge Qgd 9.4 14 nC
Gate Plateau Voltage Vplateau -3.4 V
Drain-Source Diode Characteristics (7)
Parameter Symbol Test Condition Min Typ Max Unit
Body Diode Reverse Recovery Time trr IS = -20A, di/dt = 100A/µs 69 ns
Body Diode Reverse Recovery Charge Qrr TJ = 25°C 87 nC
Diode Forward Current IS TA = 25°C -190 A

Notes:

  1. This current is chip limited, which is calculated based on RθJC.
  2. This current is calculated on single pulse with 10µs Pulse.
  3. Defined by design, not subject to production test. TJ=25°C, VDS=-20V, VGS=-10V, L=1.0mH.
  4. Device mounted on FR-4 substrate PC board with 2oz copper in 1inch square cooling area.
  5. Thermal resistance from junction to the exposed pad.
  6. Short duration pulse test used to minimize self-heating effect.
  7. Defined by design; not subject to production.