SMP4010ALUQ product image

Product Detail

SMP4010ALUQ

SineSemi 中晶新源Core Authorized Distributor

LV & MV MOSFETsAutomotiveTO252-3L

Specifications

Package
TO252-3L
VDS_Max
-40 V
ID
-76 A
Automotive (Y/N)
Y
VGS(th)_Typ
-1.8 V
RDS(ON)_Typ @VGS=4.5V
10.3 mΩ
RDS(ON)_Max @VGS=4.5V
13.4 mΩ
VGS_Max
±20 V
Tj
175 °C
EAS_Max
212 mJ
Ciss_Typ
1511 pF
Coss_Typ
1077 pF
Crss_Typ
76 pF
Qg_Typ
24 nC

Online Datasheet

Compiled from the manufacturer's datasheet; the official document prevails.

SMP4010ALUQ

-40V P-Channel Enhancement Mode Power MOSFET

Sinesemi Automotive MOSFET — AEC-Q101 Qualified, PPAP Capable, 175°C Operating Temperature

Product Summary
V_DS R_DS(ON), max I_D, max
-40 V 8.9 mΩ @ V_GS = -10V -76 A
13.4 mΩ @ V_GS = -4.5V

TO252-3L

Features
  • P-Channel Enhancement Mode - Logic Level
  • AEC-Q101 Qualified, PPAP Capable
  • 175°C Operating Temperature
  • 100% ∆VDS & UIS & Rg Tested
Application
  • General Automotive Applications
Mechanical Data
  • Green Molding Compound
  • Moisture Sensitivity: Level 1 per J-STD-020
  • UL Flammability Classification Rating 94V-0
Ordering Information
Orderable Part Number Package Type Device Marking Form Quantity (pcs)
SMP4010ALUQ TO252-3L P4010ALQ 13" Tape&Reel 2,500
Maximum Ratings (@ T_A = 25°C, unless otherwise specified.)
Parameter Symbol Value Unit
Drain - Source Voltage V_DS -40 V
Gate - Source Voltage V_GS ±20 V
Continuous Drain Current (V_GS = -10V) ^(1) I_D T_A = 25°C: -76 A
T_A = 100°C: -54 A
Pulsed Drain Current ^(2) I_DM -304 A
Single Pulse Avalanche Energy ^(3) E_AS 212 mJ
Single Pulse Avalanche Current (L = 0.1mH) I_AS -35 A
Power Dissipation P_D T_A = 25°C: 83 W
T_A = 100°C: 42 W
Junction & Storage Temperature Range T_J, T_STG -55 ~ +175 °C
Thermal Characteristics
Parameter Symbol Typ Max Unit
Thermal Resistance, Junction-to-Ambient ^(4) R_θJA 35 43 °C/W
Thermal Resistance, Junction-to-Case ^(5) R_θJC 1.4 1.8 °C/W

Electrical Characteristics (@ T_J = 25°C, unless otherwise specified.)

Off Characteristics ^(7)
Parameter Symbol Test Condition Min Typ Max Unit
Drain-Source Breakdown Voltage V_(BR)DSS V_GS = 0V, I_D = -250µA -40 V
Zero Gate Voltage Drain Current I_DSS V_DS = -40V, V_GS = 0V -1.0 µA
T_J = 125°C -100 µA
Gate-Source Leakage Current I_GSS V_GS = ±20V, V_DS = 0V ±100 nA
On Characteristics ^(7)
Parameter Symbol Test Condition Min Typ Max Unit
Gate Threshold Voltage V_GS(th) V_DS = V_GS, I_D = -250µA -1.2 -1.8 -2.5 V
Static Drain-Source On-Resistance R_DS(on) V_GS = -10V, I_D = -20A 7.2 8.9
V_GS = -4.5V, I_D = -15A 10.3 13.4
Forward Transconductance g_fs V_DS = -5.0V, I_D = -20A 30 S
Diodes Forward Voltage V_SD I_S = -2.0A, V_GS = 0V -0.7 -1.2 V
Dynamic Characteristics ^(7)
Parameter Symbol Test Condition Min Typ Max Unit
Input Capacitance C_iss V_DS = -20V, V_GS = 0V, f = 1MHz 1511 1964 pF
Output Capacitance C_oss 1077 1400 pF
Reverse Transfer Capacitance C_rss 76 140 pF
Gate Resistance R_g V_GS = 0V, V_DS = 0V, f = 1MHz 12 Ω
Switching Characteristics ^(7)
Parameter Symbol Test Condition Min Typ Max Unit
Turn-On Delay Time t_d(on) V_GS = -10V, V_DS = -20V 5.6 ns
Rise Time t_r I_D = -20A, R_GEN = 3.0Ω 13 ns
Turn-Off Delay Time t_d(off) 47 ns
Fall Time t_f 26 ns
Gate Charge Characteristics ^(7)
Parameter Symbol Test Condition Min Typ Max Unit
Total Gate Charge (V_GS = -10V) Q_g V_DS = -20V, I_D = -20A 24 31 nC
Total Gate Charge (V_GS = -4.5V) Q_g 11.8 15.3 nC
Gate-Source Charge Q_gs V_GS = -10V 4.4 6.6 nC
Gate-Drain Charge Q_gd 3.9 5.7 nC
Gate Plateau Voltage V_plateau -3.1 V
Drain-Source Diode Characteristics ^(7)
Parameter Symbol Test Condition Min Typ Max Unit
Body Diode Reverse Recovery Time t_rr I_S = -20A, di/dt = 100A/µs 38 ns
Body Diode Reverse Recovery Charge Q_rr T_J = 25°C 25 nC
Diode Forward Current I_S T_A = 25°C -76 A

Notes:

  1. This current is chip limited, which is calculated based on RθJC.
  2. This current is calculated on single pulse with 10µs Pulse.
  3. Defined by design, not subject to production test. T_J=25°C, V_DS=-20V, V_GS=-10V, L=1.0mH.
  4. Device mounted on FR-4 substrate PC board with 2oz copper in 1inch square cooling area.
  5. Thermal resistance from junction to the exposed pad.
  6. Short duration pulse test used to minimize self-heating effect.
  7. Defined by design; not subject to production.