SMP6025ALPQ product image

Product Detail

SMP6025ALPQ

SineSemi 中晶新源Core Authorized Distributor

LV & MV MOSFETsAutomotivePDFN5060-8L
Download Datasheet

Specifications

Package
PDFN5060-8L
Configuration
P
VDS_Max
-60 V
ID
-42 A
RDS(ON)_Max @VGS=10V
25 mΩ
Automotive (Y/N)
Y
VGS(th)_Typ
-1.8 V
RDS(ON)_Typ @VGS=10V
18 mΩ
RDS(ON)_Typ @VGS=4.5V
24 mΩ
RDS(ON)_Max @VGS=4.5V
32 mΩ
VGS_Max
±20 V
Tj
175 °C
EAS_Max
144 mJ
Ciss_Typ
1551 pF
Coss_Typ
426 pF
Crss_Typ
17 pF
Qg_Typ
24 nC
ESD
No
MPQ
5000 pcs
MOQ
50000 pcs
App: Motor Drive
Y
App: HF Power
Y
App: General Switch
Y

Package & Schematic

SMP6025ALPQ package outline, pin configuration and schematic
Package outline · Pin configuration · Schematic (from SineSemi official datasheet)

Online Datasheet

Compiled from the manufacturer's datasheet; the official document prevails.

SMP6025ALPQ

-60V P-Channel Enhancement Mode Power MOSFET

Sinesemi Automotive MOSFET — AEC-Q101 Qualified, PPAP Capable, 175°C Operating Temperature

Product Summary
VDS RDS(ON), max ID, max
-60 V 25 mΩ @ VGS = -10V -42 A
32 mΩ @ VGS = -4.5V

PDFN5060-8L

Features
  • P-Channel Enhancement Mode - Logic Level
  • AEC-Q101 Qualified, PPAP Capable
  • 175°C Operating Temperature
  • 100% ΔVDS & UIS & Rg Tested
Application
  • General Automotive Applications
Ordering Information
Orderable Part Number Package Type Device Marking Form Quantity (pcs)
SMP6025ALPQ PDFN5060-8L P6025ALQ 13'' Tape&Reel 5,000
Maximum Ratings (@ TC = 25°C, unless otherwise specified.)
Parameter Symbol Value Unit
Drain - Source Voltage VDS -60 V
Gate - Source Voltage VGS ±20 V
Continuous Drain Current (VGS = -10V) (1) ID TC = 25°C: -42 A
TC = 100°C: -29.4 A
Pulsed Drain Current (2) IDM -166 A
Single Pulse Avalanche Energy (3) EAS 144 mJ
Single Pulse Avalanche Current (L = 0.1mH) IAS -33 A
Power Dissipation PD TC = 25°C: 79 W
TC = 100°C: 39 W
Junction & Storage Temperature Range TJ, TSTG -55 ~ +175 °C
Thermal Characteristics
Parameter Symbol Typ Max Unit
Thermal Resistance, Junction-to-Ambient (4) R_θJA 39 49 °C/W
Thermal Resistance, Junction-to-Case (5) R_θJC 1.5 1.9 °C/W

Electrical Characteristics (@ TJ = 25°C, unless otherwise specified.)

Off Characteristics (6)
Parameter Symbol Test Condition Min Typ Max Unit
Drain-Source Breakdown Voltage V(BR)DSS VGS = 0V, ID = -250µA -60 V
Zero Gate Voltage Drain Current IDSS VDS = -60V, VGS = 0V -1.0 µA
TJ = 125°C -100 µA
Gate-Source Leakage Current IGSS VGS = ±20V, VDS = 0V ±100 nA
On Characteristics (6)
Parameter Symbol Test Condition Min Typ Max Unit
Gate Threshold Voltage VGS(th) VDS = VGS, ID = -250µA -1.2 -1.8 -2.5 V
Static Drain-Source On-Resistance RDS(on) VGS = -10V, ID = -20A 18 25
VGS = -4.5V, ID = -15A 24 32
Forward Transconductance gfs VDS = -5.0V, ID = -20A 28 S
Diodes Forward Voltage VSD IS = -2.0A, VGS = 0V -0.7 -1.2 V
Dynamic Characteristics (7)
Parameter Symbol Test Condition Min Typ Max Unit
Input Capacitance Ciss VDS = -30V, VGS = 0V, f = 1MHz 1551 2016 pF
Output Capacitance Coss 426 554 pF
Reverse Transfer Capacitance Crss 17 34 pF
Gate Resistance Rg VGS = 0V, VDS = 0V, f = 1MHz 5.7 Ω
Switching Characteristics (7)
Parameter Symbol Test Condition Min Typ Max Unit
Turn-On Delay Time td(on) VGS = -10V, VDS = -30V 4.7 ns
Rise Time tr ID = -20A, RGEN = 3.0Ω 9.0 ns
Turn-Off Delay Time td(off) 27 ns
Fall Time tf 9.6 ns
Gate Charge Characteristics (7)
Parameter Symbol Test Condition Min Typ Max Unit
Total Gate Charge (VGS = -10V) Qg VDS = -30V, ID = -20A 24 32 nC
Total Gate Charge (VGS = -4.5V) Qg 10.0 13 nC
Gate-Source Charge Qgs VGS = -10V 5.1 7.7 nC
Gate-Drain Charge Qgd 2.2 3.3 nC
Gate Plateau Voltage Vplateau -3.4 V
Drain-Source Diode Characteristics (7)
Parameter Symbol Test Condition Min Typ Max Unit
Body Diode Reverse Recovery Time trr IS = -20A, di/dt = 100A/µs 32 ns
Body Diode Reverse Recovery Charge Qrr TJ = 25°C 27 nC
Diode Forward Current IS TC = 25°C -42 A

Notes:

  1. This current is chip limited, which is calculated based on RθJC.
  2. This current is calculated on single pulse with 10µs Pulse.
  3. Defined by design, not subject to production test.
  4. Device mounted on FR-4 substrate PC board with 2oz copper in 1inch square cooling area.
  5. Thermal resistance from junction to the exposed pad.
  6. Short duration pulse test used to minimize self-heating effect.
  7. Defined by design, not subject to production.