SMJ60R024BFY 产品图

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SMJ60R024BFY

中晶新源 SineSemi核心代理商

高压 MOSFETTO247-3L
规格书下载

参数规格

车规 (Y/N)
N
封装
TO247-3L
结构
N
结温 Tj
150 °C
漏源电压 VDS
600 V
漏极电流 ID
80 A
阈值电压 VGS(th) 典型
4 V
导通电阻 RDS(ON)@10V 典型
18.5 mΩ
导通电阻 RDS(ON)@10V 最大
24 mΩ
栅源电压 VGS 最大
±30 V
雪崩能量 EAS 最大
2880 mJ
输入电容 Ciss 典型
7212 pF
输出电容 Coss 典型
142 pF
反向传输电容 Crss 典型
29 pF
总栅极电荷 Qg 典型
221 nC

封装与电路符号

SMJ60R024BFY 封装外形、引脚配置与电路符号图
封装外形 · 引脚配置 · 电路符号(源自中晶新源官方 datasheet)

在线规格书

以下内容整理自原厂规格书,实际参数以原厂正式文件为准。

SMJ60R024BFY

600V Super Junction N-Channel Power MOSFET

Product Summary
V_DS R_DS(ON), max I_D, max
600 V 24 mΩ @ V_GS = 10V 80 A

TO247-3L

Features
  • Low On-Resistance
  • Fast Switching Capability
  • 100% ∆V/DS & UIS & R_G Tested
  • RoHS compliant, HALOGEN FREE
Applications
  • LED Lighting
  • Charger and Adapter
  • PC and Telecom Power
Mechanical Data
  • Green Molding Compound
  • Moisture Sensitivity: Level 3 per J-STD-020
  • UL Flammability Classification Rating 94V-0
Ordering Information
Orderable Part Number Package Type Device Marking Form Quantity (pcs)
SMJ60R024BFY TO247-3L 60R024BF Tube 30
Maximum Ratings (@ T_C = 25°C, unless otherwise specified.)
Parameter Symbol Value Unit
Drain - Source Voltage V_DS 600 V
Gate - Source Voltage V_GS ±30 V
Continuous Drain Current (V_GS = 10V) ^(1) I_D T_C = 25°C: 80 A
T_C = 100°C: 50 A
Pulsed Drain Current ^(2) I_DM 319 A
Single Pulse Avalanche Energy ^(3) E_AS 2880 mJ
Single Pulse Avalanche Current (L = 10.0mH) I_AS 16.3 A
Power Dissipation P_D T_C = 25°C: 379 W
T_C = 100°C: 152 W
MOSFET dv/dt Ruggedness, V_DS = 0...400V dv/dt 56 V/ns
Reverse Diodes dv/dt, V_DS = 0...400V, I_SD ≤ I_D dv/dt 26 V/ns
Junction & Storage Temperature Range T_J, T_STG -55 ~ +150 °C
Thermal Characteristics
Parameter Symbol Typ Max Unit
Thermal Resistance, Junction-to-Ambient ^(4) R_θJA 40 50 °C/W
Thermal Resistance, Junction-to-Case ^(5) R_θJC 0.25 0.33 °C/W

Electrical Characteristics (@ T_J = 25°C, unless otherwise specified.)

Off Characteristics ^(6)
Parameter Symbol Test Condition Min Typ Max Unit
Drain-Source Breakdown Voltage V_(BR)DSS V_GS = 0V, I_D = 250µA 600 V
Zero Gate Voltage Drain Current I_DSS V_DS = 600V, V_GS = 0V 1.0 µA
T_J = 125°C 100 µA
Gate-Source Leakage Current I_GSS V_GS = ±30V, V_DS = 0V ±100 nA
On Characteristics ^(6)
Parameter Symbol Test Condition Min Typ Max Unit
Gate Threshold Voltage V_GS(th) V_DS = V_GS, I_D = 250µA 3.0 4.0 5.0 V
Static Drain-Source On-Resistance R_DS(on) V_GS = 10V, I_D = 10A 18.5 24
Diodes Forward Voltage V_SD I_S = 10A, V_GS = 0V 0.8 1.2 V
Dynamic Characteristics ^(7)
Parameter Symbol Test Condition Min Typ Max Unit
Input Capacitance C_iss V_DS = 400V, V_GS = 0V, f = 250kHz 7212 pF
Output Capacitance C_oss 142 pF
Reverse Transfer Capacitance C_rss 29 pF
Effective Output Capacitance, Energy Related ^(8) C_o(er) V_GS = 0V, V_DS = 0...400V, f = 250kHz 188 pF
Effective Output Capacitance, Time Related ^(9) C_o(tr) 1327 pF
Gate Resistance R_g V_GS = 0V, V_DS = 0V, f = 1MHz 9.3 Ω
Switching Characteristics ^(7)
Parameter Symbol Test Condition Min Typ Max Unit
Turn-On Delay Time t_d(on) V_GS = 10V, V_DS = 400V 71 ns
Rise Time t_r I_D = 20A, R_GEN = 3.0Ω 62 ns
Turn-Off Delay Time t_d(off) 381 ns
Fall Time t_f 46 ns
Gate Charge Characteristics ^(7)
Parameter Symbol Test Condition Min Typ Max Unit
Total Gate Charge (V_GS = 10V) Q_g V_DS = 400V, I_D = 20A, V_GS = 10V 221 nC
Total Gate Charge (V_GS = 7.0V) Q_g 167 nC
Gate-Source Charge Q_gs 46 nC
Gate-Drain Charge Q_gd 104 nC
Gate Plateau Voltage V_plateau 6.1 V
Drain-Source Diode Characteristics ^(7)
Parameter Symbol Test Condition Min Typ Max Unit
Body Diode Reverse Recovery Time t_rr I_S = 20A, di/dt = 100A/µs, T_J = 25°C 258 ns
Body Diode Reverse Recovery Charge Q_rr 1.5 µC
Body Diode Reverse Recovery Current I_RRM 8.3 A
Diode Forward Current I_S T_C = 25°C 80 A

Notes:

  1. This current is chip limited, which is calculated based on RθJC.
  2. This current is calculated on single pulse with 10µs Pulse & Duty Cycle = 1%.
  3. Defined by design, not subject to production test. T_J=25°C, V_DD=400V, V_GS=10V, L=50mH.
  4. Device mounted on FR-4 substrate PC board with 2oz copper in 1inch square cooling area.
  5. Thermal resistance from junction to the exposed pad.
  6. Short duration pulse test used to minimize self-heating effect.
  7. Defined by design; not subject to production.
  8. C_o(er) is a fixed capacitance that gives the same stored energy as C_oss while V_DS is rising from 0 to 400V.
  9. C_o(tr) is a fixed capacitance that gives the same charging time as C_oss while V_DS is rising from 0 to 400V.