SYN9N50
500 V N-Channel Power MOSFET
DATASHEET
Features
- VDSS = 500 V, ID = 9 A
- RDS(ON)_TYP = 0.66 Ω (VGS = 10 V)
- Low RDS(ON)
- Low Gate Charge
- 100% Avalanche Tested
Applications
- LED Power Supplies
- Switch-Mode Power Supplies
- Motor Driving
N-channel enhancement-mode power MOSFET built on VDMOS technology, combining low RDS(ON) with low gate charge. Available in TO-220F, TO-263 and TO-252 packages.
Pin Configuration
| Terminal |
Description |
| G |
Gate |
| D |
Drain (tab) |
| S |
Source |
Ordering Information
| Orderable Part Number |
Package |
Marking |
| SYN9N50F |
TO-220F |
SYN9N50F |
| SYN9N50S |
TO-263 |
SYN9N50S |
| SYN9N50D |
TO-252 |
SYN9N50D |
Absolute Maximum Ratings
（@ TC = 25 °C, unless otherwise specified. 按封装分列，未分列的值三封装共用。）
| Parameter |
Symbol |
SYN9N50F |
SYN9N50S |
SYN9N50D |
Units |
| Drain – Source Voltage |
VDSS |
500 |
500 |
500 |
V |
| Gate – Source Voltage |
VGS |
±30 |
±30 |
±30 |
V |
| Drain Current — Continuous (@ TC = 25 °C) |
ID |
9 |
9 |
9 |
A |
| Drain Current — Continuous (@ TC = 100 °C) |
ID |
5.7 |
5.7 |
5.7 |
A |
| Drain Current — Pulsed (1) |
IDM |
36 |
36 |
36 |
A |
| Total Power Dissipation (@ TC = 25 °C) |
PD |
30 |
198 |
178 |
W |
| Single Pulse Avalanche Energy (2) |
EAS |
352.8 |
352.8 |
352.8 |
mJ |
| Operating Junction Temperature Range |
TJ |
−55 ~ 150 |
−55 ~ 150 |
−55 ~ 150 |
°C |
| Storage Temperature Range |
TSTG |
−55 ~ 150 |
−55 ~ 150 |
−55 ~ 150 |
°C |
Thermal Characteristics
| Parameter |
Symbol |
SYN9N50F |
SYN9N50S |
SYN9N50D |
Units |
| Junction to Ambient |
RθJA |
62.5 |
62.5 |
62 |
°C/W |
| Junction to Case |
RθJC |
4.1 |
0.63 |
0.7 |
°C/W |
Electrical Characteristics
（@ TC = 25 °C, unless otherwise specified.）
Off Characteristics
| Parameter |
Symbol |
Test Conditions |
Min. |
Typ. |
Max. |
Units |
| Drain–Source Breakdown Voltage |
VDSS |
VGS = 0 V, ID = 250 μA |
500 |
— |
— |
V |
| Zero-Gate Voltage Drain Current |
IDSS |
VDS = 500 V, VGS = 0 V |
— |
— |
1 |
μA |
| Gate–Source Leakage Current |
IGSS |
VGS = ±30 V, VDS = 0 V |
— |
— |
±100 |
nA |
On Characteristics
| Parameter |
Symbol |
Test Conditions |
Min. |
Typ. |
Max. |
Units |
| Gate Threshold Voltage |
VGS(TH) |
VDS = VGS, ID = 250 μA |
2 |
— |
4 |
V |
| Drain–Source On-Resistance (3) |
RDS(ON) |
VGS = 10 V, ID = 4.5 A |
— |
0.66 |
0.85 |
Ω |
Dynamic Characteristics
| Parameter |
Symbol |
Test Conditions |
Min. |
Typ. |
Max. |
Units |
| Input Capacitance |
Ciss |
VGS = 0 V, VDS = 25 V, f = 1 MHz |
— |
1090 |
— |
pF |
| Output Capacitance |
Coss |
VGS = 0 V, VDS = 25 V, f = 1 MHz |
— |
105.6 |
— |
pF |
| Reverse Transfer Capacitance |
Crss |
VGS = 0 V, VDS = 25 V, f = 1 MHz |
— |
26 |
— |
pF |
Switching Characteristics
| Parameter |
Symbol |
Test Conditions |
Min. |
Typ. |
Max. |
Units |
| Turn-On Delay Time |
td(on) |
VGS = 10 V, VDD = 250 V, RG = 10 Ω, ID = 9 A |
— |
17.7 |
— |
ns |
| Rise Time |
tr |
VGS = 10 V, VDD = 250 V, RG = 10 Ω, ID = 9 A |
— |
52.2 |
— |
ns |
| Turn-Off Delay Time |
td(off) |
VGS = 10 V, VDD = 250 V, RG = 10 Ω, ID = 9 A |
— |
27 |
— |
ns |
| Fall Time |
tf |
VGS = 10 V, VDD = 250 V, RG = 10 Ω, ID = 9 A |
— |
8.3 |
— |
ns |
Gate Charge Characteristics
| Parameter |
Symbol |
Test Conditions |
Min. |
Typ. |
Max. |
Units |
| Total Gate Charge |
Qg |
VDS = 400 V, ID = 9 A, VGS = 10 V |
— |
22.6 |
— |
nC |
| Gate–Source Charge |
Qgs |
VDS = 400 V, ID = 9 A, VGS = 10 V |
— |
5.4 |
— |
nC |
| Gate–Drain Charge |
Qgd |
VDS = 400 V, ID = 9 A, VGS = 10 V |
— |
9.1 |
— |
nC |
Drain–Source Diode Characteristics
| Parameter |
Symbol |
Test Conditions |
Min. |
Typ. |
Max. |
Units |
| Diode Forward Voltage |
VSD |
VGS = 0 V, ISD = 9 A |
— |
— |
1.3 |
V |
| Source Current |
IS |
TC = 25 °C |
— |
— |
9 |
A |
| Reverse Recovery Time |
trr |
IS = 9 A, dI/dt = 100 A/μs |
— |
348 |
— |
ns |
| Reverse Recovery Charge |
Qrr |
IS = 9 A, dI/dt = 100 A/μs |
— |
2.97 |
— |
μC |
Typical Characteristics
原文第 3–5 页为典型特性曲线图，含下列 13 幅图（曲线为图形数据，图题嵌于图内，此处仅转写图题，未数值化）：
- Figure 1: Output Characteristics
- Figure 2: Transfer Characteristics
- Figure 3: On-Resistance vs Drain Current
- Figure 4: On-Resistance vs Junction Temperature
- Figure 5: Gate Charge
- Figure 6: Drain Current Derating
- Figure 7: Body Diode Forward Characteristics
- Figure 8: Capacitance vs Drain–Source Voltage
- Figure 9: Maximum Safe Operating Area
- Figure 10: Power Dissipation Derating
- Figure 11: Breakdown Voltage vs Junction Temperature
- Figure 12: Threshold Voltage vs Junction Temperature
- Figure 13: Maximum Transient Thermal Impedance
Package Outline Dimensions (TO-220F, unit: mm)
| Symbol |
Min. |
Nom. |
Max. |
| A |
4.42 |
4.7 |
5.02 |
| A1 |
2.3 |
2.54 |
2.8 |
| A3 |
2.5 |
2.76 |
3.1 |
| b |
0.7 |
0.8 |
0.9 |
| b2 |
— |
— |
1.47 |
| c |
0.35 |
0.5 |
0.65 |
| D |
15.25 |
15.87 |
16.25 |
| D1 |
15.3 |
15.75 |
16.3 |
| D2 |
9.3 |
9.8 |
10.3 |
| E |
9.73 |
10.16 |
10.36 |
| e |
|
2.54 BSC |
|
| H1 |
6.4 |
6.68 |
7 |
| L |
12.48 |
12.98 |
13.48 |
| L1 |
— |
— |
3.5 |
| øP |
3 |
3.18 |
3.4 |
Package Outline Dimensions (TO-263, unit: mm)
| Symbol |
Min. |
Nom. |
Max. |
| A |
9.8 |
10 |
10.4 |
| B |
8.9 |
— |
9.5 |
| B1 |
0 |
— |
0.1 |
| C |
4.4 |
4.5 |
4.8 |
| D |
1.16 |
1.4 |
1.5 |
| E |
0.7 |
0.75 |
0.95 |
| F |
0.3 |
0.45 |
0.6 |
| G |
1.07 |
1.38 |
1.47 |
| H |
1.3 |
— |
1.8 |
| K |
0.95 |
1 |
1.37 |
| L1 |
14.5 |
15.2 |
16.5 |
| L2 |
1.6 |
2 |
2.3 |
| I |
0 |
— |
0.2 |
| Q |
0° |
3° |
8° |
| R |
|
0.4 |
|
| N |
2.35 |
2.4 |
2.7 |
Package Outline Dimensions (TO-252, unit: mm)
| Symbol |
Min. |
Nom. |
Max. |
| A |
6.3 |
6.5 |
6.9 |
| A1 |
0 |
— |
0.16 |
| B |
5.7 |
— |
6.3 |
| C |
2.1 |
2.3 |
2.5 |
| D |
0.3 |
0.5 |
0.7 |
| E1 |
0.6 |
0.65 |
0.9 |
| F |
0.3 |
0.5 |
0.6 |
| G |
0.7 |
0.9 |
1.2 |
| L1 |
9.6 |
10 |
10.5 |
| L2 |
2.7 |
— |
3.1 |
| H |
0.4 |
— |
1 |
| M |
5.1 |
5.2 |
5.5 |
| N |
2.09 |
2.2 |
2.49 |
| R |
|
0.3 |
|
| T |
1.4 |
— |
1.6 |
| Y |
5.1 |
5.9 |
6.3 |
Notes
- TC = 25 °C; pulse width limited by maximum junction temperature.
- EAS condition: starting TJ = 25 °C, L = 30 mH, Rg = 25 Ω.
- Pulse test: pulse width ≤ 300 μs, duty cycle ≤ 2%.
Important Notice
Information in this document is provided in connection with 突触半导体 products and is subject to change without notice. Customers are responsible for verifying that the product is suitable for their application; no license to any intellectual property right is granted by this document.
SYN9N50 · Rev 1.1 · 2026-07 深圳市突触半导体有限公司 · synapsechip.com Page 1–6 of 6
